1. Field
The following description relates to a low-density parity-check (LDPC) code decoder and method for reducing memory usage.
2. Description of Related Art
A low-density parity-check (LDPC) code decoder typically involves a large number of operations. Accordingly, the LDPC code decoder is generally implemented as a single instruction multiple data (SIMD)-class application specific integrated circuit (ASIC). However, there are various LDPC standards which have been established. As a result, developing ASIC-type LDPC code decoders that are compliant to each of the standards can cause the decoder to be quite inefficient.
To flexibly respond to various standards, an application specific instruction processor (ASIP) is needed. However, ASIPs struggle when processing a relatively large amount of data. Also, it is difficult to implement an ASIC-type LDPC code decoder due to low compatibility.